In order to efficiently transfer an odd number of byte data by using a DMAC (Direct Memory Access Controller), an approach has been proposed in which only one byte among the last two-byte data is output to a transfer destination. This type of DMAC used in transfer of an odd number of byte data transfers an even or odd number of data to a data buffer in response to a transfer request. For example, related arts are discussed in Japanese Laid-open Patent Publication Nos. 2007-334600, 07-334454 and 2003-281074.
However, an approach has not been disclosed yet in which an odd number of byte data is transferred by using a DMAC capable of transferring only even number of byte data. In particular, in a data transfer device wherein only valid data is transferred from a DMAC capable of transferring only even number of byte data, an approach to transfer an odd number of byte data has not been disclosed yet.